MediaTek recruits former TSMC CoWoS driver Yu Zhenhua: says it has nothing to do with Intel EMIB, and chooses TSMC over others

MediaTek announced on May 2 that it has recruited Yu Zhenhua, former TSMC R&D vice president, to serve as a non-full-time adviser. His responsibilities focus on exploring advanced packaging technologies and path planning, and further deepening cooperation with TSMC’s advanced packaging products. MediaTek also issued a simultaneous statement saying that this move is “unrelated to Intel EMIB,” publicly tying its advanced packaging roadmap to TSMC. Yu Zhenhua is a key driver of CoWoS with 31 years of experience at TSMC, and the last retired elder among TSMC’s “R&D six knights.”

5/2 statement sets the tone: MediaTek clearly cuts ties with Intel EMIB, chooses TSMC

There were rumors that MediaTek might follow Intel’s EMIB-T packaging roadmap being evaluated alongside Google TPU v9, but in its May 2 announcement, MediaTek explicitly stated: “This has nothing to do with Intel EMIB. The company invests in multiple advanced packaging technology solutions and will work closely with partners across multiple packaging paths to provide customers with the best方案.” This stance effectively publicly chooses TSMC in the CoWoS-versus-Intel EMIB contest, and it also responds to earlier market speculation about potential shifts by ASIC vendors toward Intel EMIB.

The recruitment of Yu Zhenhua, the main CoWoS driver, has been interpreted by the market as a dual signal: first, MediaTek is building its own advanced packaging expertise and will no longer rely entirely on TSMC’s one-way supply; second, it is tying itself more closely to TSMC—securing priority CoWoS capacity by deploying real headcount.

A source cited by Free Finance indicates that TSMC previously believed “customers won’t leave,” but TPU v9 indeed involves discussions of migration. TSMC therefore must take a more proactive posture to retain key customers.

Who is Yu Zhenhua: CoWoS driver, 1,500 U.S. patents, and a retired elder of TSMC’s R&D six knights

Yu Zhenhua was born in 1955. He earned a bachelor’s degree in physics from National Chiao Tung University and a Ph.D. in materials engineering from Georgia Institute of Technology in the United States. He joined TSMC’s R&D division in 1994. Over his 31-year tenure, he accumulated more than 1,500 U.S. patents, received the “Morris Chang Ph.D. Award” four times, and was elected an academician of Academia Sinica. He is the last retired elder among TSMC’s “R&D six knights.” On July 8, 2025, he stepped down from the vice president position, with Guo Jinjun taking over.

Yu Zhenhua’s most critical contribution to advanced packaging is his lead in driving CoWoS technology. He himself previously said: “Without CoWoS packaging technology, generative AI is hard to come out.” This technology has become the core bottleneck in the mass production of today’s AI chips. Semiconductor analysts generally believe that advanced packaging will be the most persistent bottleneck in the AI industry over the next three years. TSMC’s target CoWoS monthly production capacity of 115k units by the end of 2026 is still expected to be in short supply.

Motivation: MediaTek’s ASIC business is ramping up, and the Google TPU large order is already in hand

The timing of MediaTek recruiting Yu Zhenhua is directly tied to the ramp-up of its data center ASIC business. MediaTek confirmed on 4/27 that it has secured the Google 8th-generation TPU order (TPU 8t). It will use TSMC’s N3P process and CoWoS-S advanced packaging, with revenue contribution expected to begin in Q4 2026. Legal/financial analysts estimate that MediaTek’s data center ASIC revenue in 2026 will exceed $1 billion, move toward the billions of dollars in 2027, and challenge a 15% ASIC market share.

In its earnings conference, MediaTek disclosed that it is simultaneously investing in two types of advanced packaging solutions and is confident it can deliver high-yield output. In the process of ASIC business evolving from “a theme” to “actual revenue contribution,” the level of technical mastery of packaging paths directly affects delivery risk and gross margin room. MediaTek’s statement emphasizes that Yu Zhenhua will “guide the company in deepening R&D and investment into TSMC’s advanced packaging products,” meaning it internalizes bargaining power and technical understanding at the packaging end rather than simply outsourcing it to contract manufacturers. The next point to watch is whether on 5/7 MediaTek will further disclose its ASIC and packaging blueprint in subsequent earnings calls or industry events, as well as the final packaging decision for Google TPU v9 (with a 2027 mass production target).

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