As demand for AI chips continues to drive tight capacity for advanced packaging, Intel’s EMIB packaging technology is once again in the spotlight. Tech media Wccftech cites the remarks of Jeff Pu, a technology research analyst at GF Securities, saying that Intel EMIB’s yield has reached 90%. This suggests that the advanced packaging technology—viewed as a key piece in Intel’s transformation to Intel Foundry—has achieved the maturity needed for further adoption of AI data center chips.
(Chen Liwu wields divine power! Citrini calls Intel “best earnings report this year,” hoping it can pick up on TSMC CoWoS spillover demand)
This also echoes Citrini Research’s prior view on Intel: Intel may not need to immediately defeat TSMC across the board on leading-edge processes, but with TSMC’s CoWoS continuing to be in short supply, Intel’s EMIB and Foveros have the chance to absorb spillover demand for AI ASIC, chiplet, and HBM packaging—becoming a “relief valve” in the AI supply chain.
EMIB yield reaches 90%, and a key puzzle piece for the Intel Foundry transition emerges
Wccftech reports that Intel EMIB is regarded as one of the company’s most critical foundry and advanced packaging technologies. Its role is to offer a 2.5D packaging alternative that is more cost-effective than TSMC CoWoS and easier to scale.
EMIB, short for Embedded Multi-die Interconnect Bridge, is Intel’s embedded multi-die interconnect bridge technology. Unlike traditional 2.5D packaging that uses a large silicon interposer layer, EMIB connects multiple dies or chiplets through small silicon bridges embedded in the packaging substrate. Intel claims this design can reduce the use of additional silicon area, improve yield, lower power consumption and costs, and make it easier to integrate chips from different process nodes and different IP blocks into a single package.
Wccftech notes that Jeff Pu said Intel EMIB’s yield has reached 90%. This is an important positive for Intel Foundry and also explains why market confidence in Intel Foundry has recently started to rebound. The report also mentions that Google’s next-generation TPU is rumored to use Intel’s advanced packaging, NVIDIA’s next-generation Feynman chips have also been linked by market rumors to EMIB technology, and Meta has been singled out as potentially using EMIB in CPU plans in the late part of 2028.
Citrini: The real bottleneck in the AI supply chain isn’t just GPUs, but advanced packaging
This is exactly Citrini Research’s core reason for being bullish on Intel. Citrini previously listed “advanced packaging” as one of its major transaction themes for 2026, and pointed out that the market in the past often simplified AI semiconductor competition into NVIDIA vs. ASIC, TSMC vs. Intel, or Blackwell vs. TPU. But this framework overlooks a deeper bottleneck: regardless of which kind of AI chip ultimately wins, advanced packaging is required.
Google TPU, Amazon Trainium, Meta MTIA, and even custom chips OpenAI may launch in the future will all move toward architectures with multiple dies, multiple chiplets, and multiple HBM stacks. These chips are not completely substitutable for one another; instead, they jointly consume limited advanced packaging capacity.
Therefore, Citrini believes Intel’s opportunity is not to immediately outpace TSMC in leading-edge process technology, but to leverage EMIB and Foveros to capture AI packaging demand spilling over as TSMC’s CoWoS remains oversubscribed. In other words, the chips themselves can be manufactured by TSMC or Samsung, but once they enter Intel’s advanced packaging process, Intel will regain a position in the AI supply chain.
EMIB-M and EMIB-T: One prioritizes efficiency, the other is built for ultra-large AI chips
Wccftech further outlines Intel’s two key EMIB pathways: EMIB-M and EMIB-T. EMIB-M focuses on efficiency. MIM capacitors are added into its silicon bridge—i.e., Metal-Insulator-Metal capacitor—to improve power supply quality, reduce noise, and enhance power integrity. While the cost of MIM capacitors is slightly higher than that of standard metal-oxide-metal capacitors, they offer better stability and lower leakage, making them suitable for chiplet packaging that needs high-bandwidth interconnects and stable power.
EMIB-T is designed for even larger-scale AI chips. It introduces TSV—through-silicon via technology—into the EMIB bridge so that power and signals can be transmitted vertically directly through the EMIB bridge, rather than routing power around the bridge structure like EMIB-M. This makes EMIB-T more suitable for high-performance AI chips, especially data center chips that need to integrate large amounts of HBM, multiple compute chiplets, and more complex interconnect architectures. Simply put, EMIB-M addresses efficiency and power stability, while EMIB-T targets ultra-large AI packaging.
In 2028, challenges exceed 12x reticle size—Intel aims to catch up to hyperscaler AI chip demand
Wccftech reports that currently, EMIB-T can support chip expansion beyond 8x reticle size, integrating 12 HBM and 4 high-density chiplets in a 120 x 120 package, as well as more than 20 EMIB-T connections. By 2028, Intel plans to expand EMIB-T to beyond 12x reticle size, with package sizes exceeding 120 x 180, and capable of accommodating more than 24 HBM die and more than 38 EMIB-T bridging.
This goal directly targets the hyperscaler AI chip era. As cloud giants like Google, Amazon, Meta, and Microsoft invest in custom AI ASICs, package area for a single chip will continue to grow, and the number of HBM units will keep increasing. Competition for AI chips is no longer only about single-GPU performance, but whether the entire package can accommodate more compute dies, more HBM, and more interconnects—while keeping yield, power consumption, and costs controllable.
Wccftech also mentions that TSMC is expected to reach 14x reticle size by 2028 and integrate up to 20 HBM packages. In addition, TSMC also has ultra-large packaging solutions such as SoW (System on Wafer), but its cost is higher than standard CoWoS.
That means Intel still faces competitive pressure. TSMC remains the leader in advanced packaging, but if Intel EMIB can penetrate the market with higher yields, lower costs, and more flexible heterogeneous integration capabilities, the market will naturally reassess Intel’s value in the AI packaging supply chain.
Intel doesn’t just have to rely on 18A—advanced packaging may bring it back to the table
In the past, when discussing Intel’s transition, the focus was mostly on the progress of the 18A process, whether the foundry business could win external customers, and whether Intel has a chance to catch up to TSMC. However, Citrini’s view is more pragmatic: Intel’s first step to return to the AI supply chain playing field doesn’t necessarily mean overtaking TSMC across the board in advanced process technology—it could start with advanced packaging.
This is especially important for Intel. AI data center demand has historically driven mainly GPUs and HBM, but as cloud giants invest in custom AI ASICs, AI chips are moving toward multi-die, multi-chiplet, multi-HBM architectures. Server CPUs, custom ASICs, HBM, and advanced packaging are all being repriced by the market together. In other words, the bottleneck in the AI supply chain is no longer just “who has the strongest GPU,” but “who can effectively package more compute chips and memory together.”
This also explains why, after Intel’s earnings report, Citrini described it as potentially “one of the best earnings reports this year.” If the claim that EMIB yield has reached 90% can be validated by customers, Intel will have the opportunity to prove to hyperscalers, AI ASIC design companies, and large chip customers that it is not only a process technology follower, but could also become an alternative supplier for advanced packaging.
In short, EMIB’s significance is no longer just an internal Intel technology showcase—it could become a concrete lever for Intel to tap into spillover demand for AI packaging. With EMIB-M strengthening power delivery efficiency, EMIB-T introducing TSV, and targeting larger and larger packaging sizes, Intel is trying to move EMIB from an existing packaging technology used in current products to a mega-scale packaging platform needed for hyperscaler AI chips in 2028.
For Intel, the real breakthrough may not be immediately beating TSMC, but rather becoming a key alternative solution in the global AI packaging capacity shortage at a time when CoWoS is oversubscribed and AI chips are fully becoming chiplet-based.
This transaction theme involves more than just Intel itself. Citrini previously pointed out that if AI ASIC and chiplet architectures continue to expand, beneficiaries could extend across the entire advanced packaging ecosystem, including packaging and equipment companies such as Amkor, Kulicke & Soffa, BESI, and others. In other words, the market may not be betting solely on a single company’s comeback; rather, it’s an opportunity to reprice the advanced packaging supply chain after AI chip architectures change.
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