Gate News message, April 24 — DeepSeek released the V4 model card today, validating earlier architectural predictions made through analysis of the TileKernels kernel library released yesterday (April 23). According to monitoring by Beating, three core components were confirmed: mHC (Manifold-Constrained Hyper-Connections) replacing ByteDance’s original HyperConnection, MoE architecture with Top-k expert routing, and FP4+FP8 mixed-precision weight storage. The predicted Engram conditional memory module did not appear in the model card.
The model card revealed new components not covered in TileKernels: hybrid attention mechanisms (CSA + HCA) drive V4’s long-context efficiency gains, reducing inference FLOPs to just 27% of V3.2’s level at 1M context windows and KV cache to 10%. Training now uses the Muon optimizer.
The verification demonstrates how production-level kernel implementations can reveal underlying model architecture before official specifications are published.
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